1. Field of the Invention
The present invention generally relates to processes for compressing geometrical data and, more particularly, to processes for compressing data relating to geometrical structures such as layouts of integrated circuits.
2. State of the Art
Modern integrated circuits, including application-specific integrated circuits of the LSI (large scale integration) or VLSI (very large scale integration) class, normally are comprised of many thousands of individual functional blocks. For instance, functional blocks in integrated circuits may comprise random access memories (RAMs), read-only memories (ROMs), or arithmetic logic units (ALUs). Also, functional blocks may be as simple as individual logic gates.
It is well known that computer-aided design (CAD) tools can be used for designing application-specific integrated circuits (ASICs). When designing and fabricating such circuits, information must be provided as to the layouts of the circuits. In practice, layouts of integrated circuits can comprise arrays of millions of polygonal shapes. The locations of individual polygonal shapes within the layouts are customarily described by specifying the locations of the vertices of the polygons. Because a high degree of precision is required when describing layouts of integrated circuits, the coordinates of the vertices of the polygonal shapes must each have a relatively large number of significant digits. Thus, in ordinary practice, very large quantities of numeric information are required to describe layouts of large integrated circuits.
Although layout information for integrated circuits can be manipulated quickly by modern computers such as engineering work stations, the communication of layout information from on location to another through normal telecommunication channels is slow and costly. For example, communication of the layout of a typical VLSI circuit over conventional telephone lines (i.e., via a modem) can take many hours. Accordingly, there exists a need for a process for compressing data describing the layout of integrated circuits so that the layout information can be readily communicated over conventional telephone lines at substantially increased speeds and, hence, at substantially reduced cost.